Prasanth Pushparasah
Data Scientist
43 years old
Driving License
Noisy-le-Grand (93160) France
Available soon
Available
Worked as electronic engineer for more than 14 years. Seeing difficulties of the semiconductor market I decided to retrain in Data Science. Currently finalizing a MSc in Applied Data Science and Big Data at DSTI, preparing also AWS, SAS and PMP certifications. Open to any opportunity in Data Science Starting November.
Memory Flow and Methodology
IMC Intel Mobile Communications
Since August 2013
Full-time
Sophia Antipolis
France
- Memory Flow and Methodology Team Leader: project scheduling, resource management
- Memory Compiler Characterization methodology: specification and flow implementation
- Memory Compiler Back-End qualification: methodolgy specification and flow implementation
- Memory Generator: development methodology specification
- Memory Compiler Physical Integration into SoC: methodology definition and tool implementation
- PDK integration in memory projects
- Flow supports to memory designers
- Flow training's for users
Senior IC Designer
IMC Intel Mobile Communications
July 2011
to July 2013
Full-time
Sophia Antipolis
France
- Memory bit-cells (RAM/ROM/RF) statistical studies (MPP Algorithms)
- Memory sense amplifier tuning based on statistical studies (MPP Algorithms)
- Memory compilers critical-path implementations (RAM/ROM)
- Memory compilers characterizations and timing tables generations
Senior Layout Mask Designer
Infineon Technologies
July 2009
to July 2011
Full-time
Sophia Antipolis
France
- Floorplanning and Full Custom Layouts for embedded memories (SPSRAM, DPSRAM, ROM, EFUSE)
- Advanced knowledge in MOS technologies : 130nm, 90nm, 65nm, 40nm, 28nm
- Memory Generators Development (Physical and Netlist)
- Back-end Qualifications (DRC, LVS, ERC, AntenaDRC, NETCHECKS, ESDNet)
- Electro-migration and IR drop studies
- SKILL programation ( Cadence programation language)
- Memory Compiler releases and supports for EDA View generations
Layout Mask Designer
Infineon Technologies
May 2003
to July 2009
Full-time
Sophia Antipolis
France
- Floorplanning and Full Custom Layouts for embedded memories (SPSRAM, DPSRAM, ROM, EFUSE)
- Advanced knowledge in MOS technologies : 130nm, 90nm, 65nm, 40nm, 28nm
- Memory Generators Development (Physical and Netlist)
- Back-end Qualifications (DRC, LVS, ERC, AntenaDRC, NETCHECKS, ESDNet)
- Electro-migration and IR drop studies
- SKILL programation ( Cadence programation language)
Part Time Waiter
Disneyland Resort Paris
June 2000
to May 2003
- Part Time Waiter (Week-End and School Vacations)
