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Prasanth Pushparasah

Prasanth Pushparasah

Data Scientist

43 years old
Driving License
Noisy-le-Grand (93160) France
Available soon Available
Worked as electronic engineer for more than 14 years. Seeing difficulties of the semiconductor market I decided to retrain in Data Science. Currently finalizing a MSc in Applied Data Science and Big Data at DSTI, preparing also AWS, SAS and PMP certifications. Open to any opportunity in Data Science Starting November.
Resume created on DoYouBuzz

Memory Flow and Methodology

IMC Intel Mobile Communications
Since August 2013
Full-time
Sophia Antipolis
France
  • Memory Flow and Methodology Team Leader: project scheduling, resource management
  • Memory Compiler Characterization methodology: specification and flow implementation
  • Memory Compiler Back-End qualification: methodolgy specification and flow implementation
  • Memory Generator: development methodology specification
  • Memory Compiler Physical Integration into SoC: methodology definition and tool implementation
  • PDK integration in memory projects
  • Flow supports to memory designers
  • Flow training's for users

Senior IC Designer

IMC Intel Mobile Communications
July 2011 to July 2013
Full-time
Sophia Antipolis
France
  • Memory bit-cells (RAM/ROM/RF) statistical studies (MPP Algorithms)
  • Memory sense amplifier tuning based on statistical studies (MPP Algorithms)
  • Memory compilers critical-path implementations (RAM/ROM)
  • Memory compilers characterizations and timing tables generations

Senior Layout Mask Designer

Infineon Technologies
July 2009 to July 2011
Full-time
Sophia Antipolis
France
  • Floorplanning and Full Custom Layouts for embedded memories (SPSRAM, DPSRAM, ROM, EFUSE)
  • Advanced knowledge in MOS technologies : 130nm, 90nm, 65nm, 40nm, 28nm
  • Memory Generators Development (Physical and Netlist)
  • Back-end Qualifications (DRC, LVS, ERC, AntenaDRC, NETCHECKS, ESDNet)
  • Electro-migration and IR drop studies
  • SKILL programation ( Cadence programation language)
  • Memory Compiler releases and supports for EDA View generations

Layout Mask Designer

Infineon Technologies
May 2003 to July 2009
Full-time
Sophia Antipolis
France
  • Floorplanning and Full Custom Layouts for embedded memories (SPSRAM, DPSRAM, ROM, EFUSE)
  • Advanced knowledge in MOS technologies : 130nm, 90nm, 65nm, 40nm, 28nm
  • Memory Generators Development (Physical and Netlist)
  • Back-end Qualifications (DRC, LVS, ERC, AntenaDRC, NETCHECKS, ESDNet)
  • Electro-migration and IR drop studies
  • SKILL programation ( Cadence programation language)

Part Time Waiter

Disneyland Resort Paris
June 2000 to May 2003
  • Part Time Waiter (Week-End and School Vacations)

MSc in Applied Data Science and Big Data

DSTI

March 2018 to October 2018
Data Science school, Understand, analyze, design, implement and monitor major IS architectures for Big Data

Bachelor Degree

ESTE

September 2000 to June 2004
Group ESIEE Paris, section ESTE Microelectronic.
  • Statistical Studies
    Good
  • Data Wrangling
    Advanced
  • Machine Learning
    Intermediate
  • Data Analysis
    Intermediate
  • Times Series Analysis
    Intermediate
  • Semantic Web
    Intermediate
  • Artificial Neural Networks
    Intermediate
  • Hadoop
    Intermediate
  • Agent Based Modeling
    Intermediate
  • Survival Analysis using R
    Intermediate
  • Deep Learning on GPR
    Intermediate
  • PERL
    Advanced
  • TCL
    Advanced
  • C
    Good
  • C++
    Good
  • SKILL (Cadence Programming Language)
    Good
  • R
    Good
  • Python
    Good
  • Shell Scripting
    Good
  • SQL
    Good
  • Matlab
    Good
  • SAS
    Good
  • HTML
    Good
  • PHP
    Good
  • Java
    Good
  • Project Planning
    Expert
  • Resource Allocation
    Advanced
  • Priority Definition
    Advanced
  • Cadence Virtuoso
    Schematic Composer / Layout / Layout-XL / ADE / ADE-XL
    Expert
  • Cadence Assura
    Physical Verifications (DRC, LVS, Antena, Latch-Up, etc...), Parasitic Extractions
    Expert
  • Synopsys IC Validator
    Physical Verifications (DRC, LVS, Antena, Latch-Up, etc...)
    Expert
  • Synopsys StarRC
    Parasitic Extractions
    Expert
  • Mentor Graphics Calibre
    Physical Verifications (DRC, LVS, Antena, Latch-Up, etc...)
    Expert
  • ANSYS Totem
    Electromigration and IR-Drop analysis
    Expert
  • 130nm (TSMC)
    Expert
  • 90nm (TSMC)
    Expert
  • 65nm (TSMC)
    Expert
  • 40nm (TSMC, UMC, Global Foundry)
    Expert
  • 28nm (TSMC, UMC, Global Foundry)
    Expert
  • 22nm(INTEL FinFet)
    Expert
  • 14nm(INTEL FinFet)
    Expert
  • 10nm(INTEL FinFet)
    Expert
  • Expert
  • Like playing MMORPG when I have time
  • Playing football with corporate team
  • Playing tennis for 20 years
  • Playing squash with corporate team
  • Like all sports in general
  • Like going out with friends and colleagues to drink a beer after work
  • Movies and Serials coming from US