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Maxim Verbitskiy

Maxim Verbitskiy

FPGA designer/ Design Verificator

36 years old
Driving License
Minsk (220019) Belarus
Employed Open to opportunities
  • Design verification with UVM (SystemVerilog) - PCIe (Gen3, Gen4) block level verification, APB periferals block level verification, design-specific subblocks verification
  • VCS simulator
Company Description
R&D center of SKHynix in Belarus
Company website