10 years of experience on advanced IC-PKG-PCB co-design. Coordinating every actor of the implementation to get a full-custom package solution with the best Performance/Cost ratio for the system. Improving the flow to help delivering the best product quality and user experience possible.
Technical expertise on chip integration and package layout, working in multicultural environment. Supporting users on tools usage, UNIX environment setup, data management and data exchange with providers and customers.
Direct relation with tool vendors (Cadence / Mentor). Providing test cases with detailed description of the process leading to the error/failure. Specification redaction and review when asking for tool enhancement, then test and validation of the solution.
Methodology creation for a package qualification test. Defining specifications with users, proposing the concept then developing and testing the PERL code. Training of the users and teammates and validation on a pilot project. Maintenance and updates for new technologies and design specificities.
Flow validation and adaptation for new silicon technology nodes. Test-chip creation using AGILE methodology to run each step of the flow and validate the existing methodology or report change requests and enhancements.
Bug tracking through UTP tickets. Scripting for task automation and flow efficency improvement. Referent for best known methods.
Detailed Description
Working with AGILE methodology on test vehicules to setup the codesign flow on new technology nodes.
System In Package implementation for digital baseband and modem SOC (in 45/40nm and 32/28nm, bulk and FD-SOI).
Close collaboration with back-end, architecture, CAD providers, PCB, SI/PI and packaging teams on multisite to provide best quality and best cost designs.
New activity for the company, strong need to interact with tool vendors and methodology team to develop the flow and improve the reliability and possibilities. Loads of test-cases and specifications exchanged with the tool developers.