Anthony Lecetre
IC assembly flow and methodology expert
Methodology enhancement
Task automation
Physical implementation
Data science
Data engineering
40 years old
Driving License
Nice France
Available soon
Available
10 years of experience on advanced IC-PKG-PCB co-design.
Coordinating every actor of the implementation to get a full-custom package solution with the best Performance/Cost ratio for the system.
Improving the flow to help delivering the best product quality and user experience possible.
Coordinating every actor of the implementation to get a full-custom package solution with the best Performance/Cost ratio for the system.
Improving the flow to help delivering the best product quality and user experience possible.
Chip-Package-Board codesign flow and methodology
Intel
October 2012
to March 2018
Sophia Antipolis
France
- Technical expertise on chip integration and package layout, working in multicultural environment.
Supporting users on tools usage, UNIX environment setup, data management and data exchange with providers and customers. - Direct relation with tool vendors (Cadence / Mentor). Providing test cases with detailed description of the process leading to the error/failure. Specification redaction and review when asking for tool enhancement, then test and validation of the solution.
- Methodology creation for a package qualification test. Defining specifications with users, proposing the concept then developing and testing the PERL code.
Training of the users and teammates and validation on a pilot project. Maintenance and updates for new technologies and design specificities. - Flow validation and adaptation for new silicon technology nodes. Test-chip creation using AGILE methodology to run each step of the flow and validate the existing methodology or report change requests and enhancements.
- Bug tracking through UTP tickets.
Scripting for task automation and flow efficency improvement.
Referent for best known methods.
IC-Package-Board codesign implementation
STMicroelectronics -- STEricson
October 2007
to October 2012
Grenoble
France
- System In Package implementation for digital baseband and modem SOC (in 45/40nm and 32/28nm, bulk and FD-SOI).
- Close collaboration with back-end, architecture, CAD providers, PCB, SI/PI and packaging teams on multisite to provide best quality and best cost designs.
- New activity for the company, strong need to interact with tool vendors and methodology team to develop the flow and improve the reliability and possibilities. Loads of test-cases and specifications exchanged with the tool developers.
IT infrastructure for Big Data.
Machine learning algorithms and data visualization.
Software development and applied mathematics.
AWS and SAS certifications.
Machine learning algorithms and data visualization.
Software development and applied mathematics.
AWS and SAS certifications.
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SOC Encounter
ESD and IRdrop aware IORing design, place and route, bumpout, RDL
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Cadence SiP
Substrate routing, embedded components implementation, PoP, stacked memories
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Cadence System Connectivity Manager (SCM)
Pinlist management
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Cadence Virtuoso
Custom RDL routing, schematic, layout
-
Calibre Mentor
DRC, GDS modifications
-
Ansys Sentinel PSI
Package voltage drop analyses, BGA modeling
- Mentor Expedition / XPI
-
PERL / PYTHON / TCL
Scripting for flow automation.
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IBM ClearCase
Version-management to improve quality and tracability.
- Unix /shell
-
ISTQB certified
Specification review, test plan creation and testing.
- Agile Methodology
- Excellent analytical and problem solving skills
-
Good communicator and sociable
Strong communication skills and very adaptive to changes.
Daily collaboration in a international context -
English speaking (fluent)
French (native)
English (fluent)
Italian (conversational)
